1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a circuit for increasing a word line potential at the time of a burn-in test (i.e., an operation test for screening cell transistors) to a value higher than at a normal operation time.
2. Description of the Related Art
A conventional word line drive circuit for semiconductor memory devices such as dynamic random access memories (DRAMs) has been provided as shown in FIG. 3. In FIG. 3, TN1 and TN2 respectively denote first and second N-channel transistors of insulated gate type (MOS type). A row decode output signal A from a row decoder (not shown) is entered in one end of the first transistor TNI, a power supply potential Vcc (for example, 5 V) is applied to the gate thereof, and the other end thereof is connected to the gate of the second transistor TN2. A word line drive control signal WDRV is applied to one end of the second transistor TN2, and a bootstrapped word line drive signal C fed from the other end thereof is supplied to a word line WL. The word line is connected to the respective gates of a large number of cell transistors (not shown).
The operation performed in a case where the row decode output signal A is at an enabled level (in this example, the power supply level Vcc of 5V) will be explained with reference to FIG. 4. In this case, the first transistor TNI is turned on, and a potential of a node B on the other end thereof (on the gate side of the second transistor TN2) becomes "Vcc-.vertline.Vtn.vertline." (Vtn is the gate threshold voltage of the first transistor TN1). The potential of the node B rises until junction breakdown is caused by the coupling of the first transistor TN1. The potential of the node B at this time becomes "V.sub.BD -.vertline.V.sub.BB .vertline." and the potential of the word line drive signal C rises as the potential of the node B is increased.
At this time, VBD is the junction breakdown voltage in N-type high impurity concentration regions acting as source and drain regions of the N-channel transistor, and V.sub.BB is a voltage for a semiconductor substrate (P-type substrate or P-type well) in which the N-channel transistors are provided. A substrate bias voltage is applied to the substrate from a substrate bias generation circuit.
For example, if the word line drive control signal WDRV is 7.5V, the junction breakdown voltage V.sub.BD is 12 V, the substrate voltage V.sub.BB is -3V and the gate threshold voltage Vtn is 1.5V, then the potential of the node B becomes approx. 9V and the word line drive signal C becomes approx. 7.5V when the power supply level Vcc is 5V.
When the power supply level Vcc is raised from 5V to 7V, for example, at the time of a burn-in test for a DRAM having the above word line drive circuit, the potential of the node B is kept at approximately 9V, which is substantially the same as the potential set at the time of a normal operation, and the word line drive signal C is at approximately 7.5V, which is substantially the same as the potential set at the time of the normal operation, and as a result, it is not possible to apply a high level word line drive signal to the cell transistors, thereby making it impossible to perform the correct screening for the cell transistors.
A substrate bias generation circuit contained in the semiconductor memory device may include a substrate potential limiting circuit for reducing current consumption caused by the operation of the substrate bias generation circuit itself. One example of such a substrate potential limiting circuit is shown in FIG. 5. The substrate potential limiting circuit includes a substrate potential detection circuit 62 for detecting the potential of a substrate 60, and a switching circuit 63 for on/off controlling the operation of a substrate bias generation circuit 61 according to the output of the substrate potential detection circuit 62.
With the substrate potential limiting circuit, when the substrate potential is lowered to reach a certain potential level, the substrate potential detection circuit 62 is operated and causes the switching circuit 63 to interrupt the operation of the substrate bias generation circuit 61, so that the substrate bias generation circuit 61 will not consume its power until the substrate potential exceeds again the threshold voltage of the substrate potential detection circuit 62.
As described above, according to the conventional semiconductor memory device, when the power supply level Vcc is raised at the time of the burn-in test, the voltage of the word line drive signal is at substantially the same level as that at the normal operation time, and the high level word line drive signal cannot be applied to the cell transistors, thereby making it impossible to perform the correct screening for the cell transistors.